A part of the circuit design process involves creating a virtual circuit representative of the intended design. This virtual circuit simulates the responses of the design to given circuit inputs. Virtual circuits may be created using any known circuit simulation software, non-limiting examples of which include Spice™.
FIG. 1 illustrates a block diagram of a virtual digital circuit 100.
As illustrated in the figure, virtual digital circuit 100 includes digital circuit portion 102, digital circuit portion 104, digital circuit portion 106 and digital circuit portion 108.
Digital circuit portion 102 is arranged to receive a digital signal 110, a digital signal 112, a digital signal 114 and a digital signal 116 and to output a digital signal 118. Digital circuit portion 104 is arranged to receive digital signal 118 and to output a digital signal 120. Circuit portion 106 is arranged to receive digital signal 118 and to output a digital signal 122. Circuit portion 108 is arranged to receive digital signal 120 and digital signal 122 and to output a digital output 124.
In operation, virtual digital circuit 100 receives a digital value from digital signal 110, digital signal 112, digital 114 and digital signal 116, and creates digital signal 124 based on the given input values. Circuit portions are smaller parts of the larger digital circuit. Digital circuit portion 102 receives a digital value from digital signal 110 through a digital input 126, a digital value from digital signal 112 through a digital input 128, a digital value from digital signal 114 through a digital input 130 and a digital value from digital signal 116 through a digital input 132. Digital circuit portion 102 outputs digital signal 118 through a digital output 134. Digital circuit portion 104 receives a digital value from digital signal 118 through a digital input 136 and outputs digital signal 120 through a digital output 140. Digital circuit portion 106 receives a digital value from digital signal 118 through a digital input 138 and outputs digital signal 122 through a digital output 142. Digital circuit portion 108 receives a digital value from digital signal 120 through a digital input 144 and receives a digital value from digital signal 122 through a digital input 146, and outputs digital signal 124 through a digital output 148.
Before proceeding to the manufacturing phase, the circuit design process includes the layout and test of a virtual circuit representative of the intended circuit design. Therefore, before a digital circuit corresponding to a virtual digital circuit can be manufactured, operation of the virtual digital circuit is tested, while in virtual operation. This is done by monitoring the states of targets in response to circuit inputs. A target can be any point, or node, in the circuit, non-limiting examples of which include, leads on a resistor and pins on an integrated circuit (IC) chip.
The targets of a digital virtual circuit are monitored using a digital checker. A digital checker can be software capable of monitoring stated targets in a virtual digital circuit. The testing portion of this process is further described in reference to FIG. 2.
FIG. 2 illustrates a conventional digital checker arranged to check virtual digital circuit 100.
A digital checker 202 is programmed to monitor states of various portions of virtual digital circuit 100. Each portion of virtual digital circuit 100 that digital checker 202 will monitor is referred to as a target. A target may be an input/output of a high level of a portion of a digital circuit, such as an amplifier. A target may be an input/output of a lower level of a digital circuit, such as a flip-flop within an amplifier. Further, a target may be an input/output of a device level portion of a digital circuit, such as a transistor in a flip-flop within an amplifier.
For purposes of explanation, in this example, presume that inputs and outputs of digital circuit portions of virtual digital circuit 100 are to be checked by digital checker 202. As illustrated in FIG. 2, digital circuit portion 102 includes a digital input 126 arranged to receive digital signal 110, a digital input 128 arranged to receive digital signal 112, a digital input 130 arranged to receive digital signal 114, a digital input 132 arranged to receive digital signal 116 and a digital output 134 arranged to output digital signal 118. Digital circuit portion 104 includes a digital input 136 arranged to receive digital signal 118 and a digital output 140 arranged to output digital signal 120. Digital circuit portion 106 includes a digital input 138 arranged to receive digital signal 118 and a digital output 142 arranged to output digital signal 122. Digital circuit portion 108 includes a digital input 144 arranged to receive digital signal 120, a digital input 146 arranged to receive digital signal 122 and a digital output 148 arranged to output digital signal 124.
As illustrated in FIG. 2, digital checker 202 is programmed such that the digital target associated with digital input 126 is arranged to be checked as represented by line 204. The digital target associated with digital input 128 is arranged to be checked as represented by line 206. Digital target associated with digital input 130 is arranged to be checked as represented by line 208. Digital target associated with digital input 132 is arranged to be checked as represented by line 210. Digital target associated with digital input 134 is arranged to be checked as represented by line 212. Digital target associated with digital input 136 is arranged to be checked as represented by line 214. Digital target associated with digital input 138 is arranged to be checked as represented by line 216. Digital target associated with digital input 140 is arranged to be checked as represented by line 220. Digital target associated with digital input 142 is arranged to be checked as represented by line 218. Digital target associated with digital input 144 is arranged to be checked as represented by line 222. Digital target associated with digital input 146 is arranged to be checked as represented by line 224. Digital target associated with digital input 148 is arranged to be checked as represented by line 226.
In operation, one input value is applied to digital input 110, one input value to digital input 112, one input value to digital input 114 and one input value to digital input 116. Since this is a digital design, input values are either 1 or 0. As each input value is applied, the states of all targets are monitored by the digital checker. For example, presume that a digital value of 1 is applied to digital input 126, a digital value of 1 is applied to digital input 128, a digital value of 0 is applied to digital input 130 and a digital value of 0 is applied to digital input 132.
Further, presume that ideally, in this example, on these provided inputs and based on the ideal operation of digital circuit portion 102, the ideal operation of digital circuit portion 104, the ideal operation of digital circuit portion 106 and the ideal operation of digital circuit portion 108, digital output 134 should have a digital value of 1, digital input 136 should have a digital value of 1, digital input 138 should have a digital value of 1, digital output 140 should have a digital value of 1, digital output 142 should have a digital value of 0, digital input 144 should have a digital value of 1, digital input 146 should have a digital value of 0 and digital output 148 should have a digital value of 1.
However, presume in this example that digital circuit portion 106 is designed incorrectly, therefore the actual digital value of output 142 is 0.
When checking digital circuit 100, digital checker 202 will check the targets as it has been preprogrammed to check. In particular, digital checker will verify that digital input 126 has a value of 1, digital input 128 has a value of 1, digital input 130 has a value of 0 and digital input 132 has a value of 0 as represented by line 204, line 206, line 208 and line 210, respectively. Digital checker 202 will verify that digital output 134 has a value of 1 as represented by line 212. Digital checker 202 will verify that digital input 136 has a value of 1 by way of line 214. Digital checker 202 will verify that digital input 138 has a value of 1 by way of line 216. Digital checker 202 will verify that digital output 140 has a value of 1 by way of line 220. Digital checker 202 will verify that digital output 142 has a value of 0 by way of line 218. Digital checker 202 will verify that digital input 144 has a value of 1 by way of line 222. Digital checker 202 will verify that digital input 146 has a value of 0 by way of line 224. Digital checker 202 will verify that digital output 148 has a value of 1 by way of line 226. Here, the lines, for example line 210, illustrates a connection that digital checker 202 would have with a target in the case where digital checker 202 is software program and digital circuit 100 is a virtual circuit, the line may be a programmed association. In the case where digital checker 202 is a device, and digital circuit 100 is a real circuit, the line may be a wired probe.
In this example, digital checker will compare the monitored value of the targets with the ideal value corresponding to the given inputs. Presume in this example that digital circuit portion 106 outputs a value of 1 as opposed to the expected value of 0. During this comparison, digital checker 202 will determine that the monitored digital value of 1 at output 142 does not correspond to the expected digital value of 0 that corresponds to the provided digital input values of 1, 1, 0, and 0 as checked by lines 204, 206, 208 and 210, respectively. In such an event, digital checker 202 will provide an indication that there is an error in virtual digital circuit 100 at output 142 and the circuit designer can take steps accordingly.
The checking process involves monitoring target states and comparing those states to the expected states corresponding to all possible input values for virtual digital circuit 100. A complete list of all possible digital input values for a virtual digital circuit to be checked is called a test bench. This is further explained using FIG. 3.
FIG. 3 illustrates an example of a digital test bench 300.
As illustrated in the figure, digital test bench 300 includes 16 possible inputs for virtual digital circuit 100.
For example, a digital input value of “0110” corresponds to digital input 110 having a value of 0, digital input 112 having a value of 1, digital input 114 having a value of 1, and digital input 116 having a value of 0. As discussed in the example above, these digital inputs are sent through virtual digital circuit 100 and the states of targets are monitored and compared with expected values corresponding to a digital input value of 0110.
Virtual digital circuit 100 of FIG. 1 is merely provided for explanation. In actuality, circuits are more complex, with many more targets and a much larger test bench. Accordingly, a pseudorandom number generator (not shown) may be used to generate pseudorandom inputs. When the pseudorandom number generator generates an input that is part of the test bench, it is noted until the entire test bench has been generated.
One of the other functions of the digital checker is to monitor the test bench. Once the test bench is created, and the digital checker is monitoring the inputs, when one of the input values included in the test bench has been given to virtual digital circuit 100 the digital checker notes that the input value has been used. FIG. 4 is used to further illustrate this function.
FIG. 4 illustrates test bench 300, after the checker has been running for a time T Specifically, in this example, assume that pseudorandom number generator has generated a plurality of pseudo random input values. Of this plurality of pseudorandom digital input values, digital input values corresponding to reference number 402, 404 and 406 have been generated. Further, and with reference to FIG. 2, digital checker 202 has verified that input value 0001 has been generated by monitoring digital input 126, digital input 128, digital input 130 and digital input 132 by way of lines 204, 206, 208 and 210, respectively. Digital checker 202 has verified that input value 0011 has been generated by monitoring digital input 126, digital input 128, digital input 130 and digital input 132 by way of lines 204, 206, 208 and 210, respectively. Digital checker 202 has verified that input value 0110 has been generated by monitoring digital input 126, digital input 128, digital input 130 and digital input 132 by way of lines 204, 206, 208 and 210, respectively. After having verified that each value is provided to these inputs, the checker notes that these input values have been used. For purposes of illustration, this is indicated with a check mark in FIG. 4.
As illustrated in FIG. 4, values “0001”, “0110” and “0011” have been checked off. This signifies that digital checker 202 has monitored all targets when digital inputs were 0001, 0110 and 0011. Since all values in the test bench have not been checked off, digital checker 202 will continue to send inputs and monitor targets. Once all values in the test bench have been checked off, digital checker 202 will stop.
However, conventional digital checkers are unable to check analog circuits.
As discussed above, each portion of a digital circuit will have a digital value at any state of either a 0 or a 1. Further, the digital checkers are only able to monitor a digital state of 0 or 1. However, each portion of an analog circuit will have one of two states, an OFF state or an ON state. Each of these states will have two different values that are distinguishable from each other.
FIG. 5 illustrates an example of an analog test bench 500 of an example analog virtual circuit.
In this example, presume that: a first bit has an OFF state associated with a value 1 and an ON state with a value of 3; a second bit has an OFF state associated with a value 2.5 and an ON state with a value of 3.1; a third bit has an OFF state associated with a value 0.5 and an ON state with a value of 7.3; and a fourth bit has an OFF state associated with a value 2.7 and an ON state with a value of 3.3. For example, the input value of item 502 of test bench 500 will have four OFF states of values of 1, 2.5, 0.5, 2.7. In this case, digital checker 202 would incorrectly recognize the first bit value of 1 as an ON state. Further, digital checker 202 would be unable to recognize values second through fourth bit values, because these values are neither a 1 or 0.
What is needed is system and method to check virtual analog circuits using a digital checkers.